Simulation of Semiconductor Lithography and Topography

Process flow simulation TCAD tools are used in this chapter to show how the planar process converts the layout into the device and interconnect structures. A good test of the working knowledge of a new process engineer or even a circuit designer is to hand them a circuit layout and ask them to sketch the device cross section. This requires an understanding of the ordering and patterning various thin-film layers during the process flow. The simulation of these structures can be carried out in seconds by extruding masks according to layer thicknesses, in minutes by adding topography 2D transition effects and step coverage simulation, or hours by including rigorous simulation of the lateral movement of dopants atoms in the silicon and/or 3D topography effects. The device and interconnect structures associated with a double level metal CMOS process for a logic chip design are used for basic illustration. Examples to explore process technology issues and their assessment with test structures are then considered. The role of the alignment process and the design/preservation of the alignment marks is emphasized. The conventions used for layout specification and typical back-of-the-envelope models used for rapid simulation are also given. Finally the issues in data structures used to describe the device topography and associated impurity doping attributes in communicating with rigorous process simulators are described.